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EVAL-CED1Z
CONNECTORS
Many connectors are provided on the CED board to facilitate
design and attachment of a range of different form factor
converter boards. Due to the number of connections available
on the FPGA, certain signals on different connectors are shared
and replicated across different connectors.
All signals have been named to assist the user in identifying the
shared signals and to which group they belong. SPI signals
begin with SPI_xxx, SPORT signals begin with SPORT_xxx and
parallel/PPI signals begin with PAR_xxx/PPI_xxx. More details
of these signals are given in the relevant connector sections.
J5 – LVDS CONNECTOR
If connecting the CED1 to a high-speed LVDS converter
evaluation board, this connector should be used. The connector
provides for four differential receive and four differential
transmit data pairs in addition to separate differential receive
Table 1. LVDS Connector pin out
Preliminary Technical Data
and transmit clocks. Control of any high-speed device is
normally achieved over an interface separate to the data. For
this purpose, the SPI and some parallel control signals are also
routed over this connector. With the inclusion of three power
supplies, this connector provides the flexibility to interface to
many LVDS converters. Details of the pin-out of this connector
are given in Table 1.
Figure 3. LVDS Connector pin locations
Pin Num
1A, 1B
1C, 1D
2A
2B
C2-9, D2-7
A3-6
B3
B4
B5
B6
A7
B7
A8
B8
A9, B9
A10, B10
C10, D10
Pin Name
+VarA
CLKOUT+/-
PAR_CS0
PAR_RD
Dx+/-
SPI_SELx
PAR_WR
SPI_MISO
SPI_MOSI
SPI_CLK
TMR0/PPI_FS2
GPIO3/TMR1/PPI_FS1
RXINT/GPIO2/PPI_FS3
GPIO4/PAR_A0
+3.3VD_Edge
+VarD
CLKIN+/-
Description
Variable voltage analog power supply. See power supply section for more details.
Differential Clock Output
Parallel Chip Select 0
Parallel Read Strobe
Differential Data Receive or Transmit Pair. By default the CED board is configured for 4
receive pairs (D0-3) and 4 transmit pairs (D4-7). These can be reconfigured by changing
the termination resistors on the CED board. See schematics for more details.
SPI Peripheral Chip Select
Parallel Write Strobe
SPI Master In, Slave Out Data line
SPI Master Out, Slave In Data line
SPI Clock
Timer 0 or Frame Sync 2 for PPI usage
General Purpose I/O, Timer 1 or Frame Sync 2 for PPI usage
Receive Interrupt, General Purpose I/O or Frame Sync 3 for PPI usage
General Purpose I/0 or parallel address LSb
+3.3V Digital power supply
Variable voltage digital power supply. See power supply section for more details.
Differential Clock Input pair
Rev. PrA | Page 4 of 24
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